Description: Apple II Hardware: 6522 Versatile Interface Adapter (2/97)
Header: Apple II Hardware: 6522 Versatile Interface Adapter (2/97)

 Article Created: 21 September 1984
 Article Reviewed/Updated: 28 February 1997

 TOPIC -----------------------------------------------------------

 This article describes the 6522 Versatile Interface Adapter (6522 VIA).

 DISCUSSION ------------------------------------------------------

 The 6522 Versatile Interface Adapter (6522 VIA) is a popular integrated
 circuit for use with microcomputers because it operates in a variety of
 modes. The precursor to the 6522, the 6520, has been used in several
 interfaces with no difficulty. Unfortunately, although these two parts have
 identical timing specifications, their operation is different. The 6520 is
 very tolerant of operation outside of the parameter limits on its data sheet
 while the 6522 must have its timing specifications met exactly.

 The most critical timing parameter for the 6522 is the address set-up time,
 the delay between the chip select and the rising edge of the 1MHz clock. The
 6522 will not operate under the nearly identical Device Select and 1 MHz
 clock of the Apple II. The solution is to shorten the positive half-cycle of
 the 1 MHz waveform. This can be achieved by various methods, but, since the
 length of the positive half-cycle is critical, it is essential to have a well-
 controlled circuit to do this.

 The circuit below is proposed for use with the Apple II. The 74LS74 circuit
 delays the positive edge of the clock by one cycle of the 7 MHz clock,
 generating the clock waveform that the 6522 needs. The negative edge of the
 clock is set by the falling edge of the 1 MHz clock; this also holds off the
 flip-flop until the next cycle. The shortened positive half-cycle of the
 clock waveform results in a leading edge delayed by 140 nanoseconds from the
 falling edge of Device Select.

 The 6522A is required to meet the data sheet timing parameters. The 6522 will
 usually work but its operation cannot be guaranteed.

                __                      __________
                  |                    |
        DEVSEL    |                    |
                  |____________________|

                _______                 __________
                       |               |
        CLOCK          |               |
                       |_______________|

 SUGGESTED SCHEMATIC

 (25) +5 -----------------+----------------------+-----------+
                     ____|___              _____|___        |
                    |    4   |   74LS74   |    10   |       |
 (40) Q0 ---------+--|2      5|------------|12      9|----+  |
                 |  |        |            |         |    |  |
 (36) 7M ------+- | -|3       |         +--|11       |    |  |
              |  |  |        |         |  |         |    |  |
              |  |  |____1___|         |  |____13___|    |  |
              |  |       |             |        |        |  |
              |  +-------+------------ | -------+        |  |
              +------------------------+                 |  |
                                                         |  |
                                             _________   |  |
 (41) DEVSEL ---------------+----------------|23     25|--+  |
 (18) R/W -------------+----|----------------|22       |     |
                     _|____|__              |       24|-----+
                    | 11   9  |             |       20|-----+
 (42) D7 ------------|19      1|-------------|26       |
 (43) D6 ------------|18      2|-------------|27       |
 (44) D5 ------------|17  8   3|-------------|28       |
 (45) D4 ------------|16  3   4|-------------|29       |
 (46) D3 ------------|15  0   5|-------------|30   6   |
 (47) D2 ------------|14  4   6|-------------|31       |
 (48) D1 ------------|13      7|-------------|32   5   |  I/O
 (49) D0 ------------|12      8|-------------|32       |  Lines:
                    |_________|             |     2   |  Port A
 ( 5) A3 ------------------------------------|35       |
 ( 4) A2 ------------------------------------|36   2   |  and
 ( 3) A1 ------------------------------------|37       |
 ( 2) A0 ------------------------------------|38   A   |  Port B
 (31) RESET ---------------------------------|34       |
 (30) IRQ -----------------------------------|21       |
                                            |_________|



 Article Change History:
 28 Feb 1997 - Reviewed for technical accuracy, revised formatting.
 Copyright 1984-97, Apple Computer, Inc.
 Keywords: